`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:11:30 05/21/2012
// Design Name:   NonPipelinedDivider
// Module Name:   /home/azonenberg/native/programming/achd-soc/trunk/hdl/achd-soc/testDivider.v
// Project Name:  achd-soc
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: NonPipelinedDivider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testDivider;

	// Inputs
	reg clk = 0;
	reg start = 0;
	reg [31:0] dend = 0;
	reg [31:0] dvsr = 0;
	reg sign = 0;

	// Outputs
	wire [31:0] quot;
	wire [31:0] rem;
	wire busy;
	wire done;

	// Instantiate the Unit Under Test (UUT)
	NonPipelinedDivider uut (
		.clk(clk), 
		.start(start), 
		.dend(dend), 
		.dvsr(dvsr), 
		.quot(quot), 
		.rem(rem), 
		.busy(busy), 
		.done(done), 
		.sign(sign)
	);

	reg ready = 0;
	initial begin
		#100;
      ready = 1;
	end
	
	always begin
		#6.25;
		clk = ready;
		#6.25;
		clk = 0;
	end
	
	reg[31:0] testcount = 0;
	always @(posedge clk) begin
		testcount <= testcount + 1;
		
		start <= 0;
		dend <= 0;
		dvsr <= 0;
		sign <= 0;
		
		if(testcount == 1) begin
			start <= 1;
			sign <= 1;
			dend <= 32'd84718;
			dvsr <= 32'd10;
		end
		
		if(start) begin
			$display("%d divided by %d is...", dend, dvsr);
		end
		
		if(done) begin
			$display("%d with a remainder of %d", quot, rem);
		end
		
	end
      
endmodule

